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74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) product specification supersedes data of 1998 feb 13 ic23 data handbook 1999 oct 18 integrated circuits
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 2 1999 oct 18 853-1842 22536 features ? 16-bit transparent latch ? 5v i/o compatibile ? 3-state buffers ? output capability: +64ma/-32ma ? ttl input and output switching levels ? input and output interface capability to systems at 5v supply ? bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs ? live insertion/extraction permitted ? power-up reset ? power-up 3-state ? no bus current loading when output is tied to 5v bus ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model description the 74alvt16373 is a high-performance bicmos product designed for v cc operation at 2.5v or 3.3v with i/o compatibility up to 5v. this device is a 16-bit transparent d-type latch with non-inverting 3-state bus compatible outputs. the device can be used as two 8-bit latches or one 16-bit latch. when latch enable (le) input is high, the q outputs follow the data (d) inputs. when latch enable is taken low, the q outputs are latched at the levels of the d inputs one setup time prior to the high-to-low transition. quick reference data symbol parameter conditions typical unit symbol parameter t amb = 25 c 2.5v 3.3v unit t plh t phl propagation delay ndx to nqx c l = 50pf 2.0 2.4 1.6 1.8 ns c in input capacitance v i = 0v or v cc 3 3 pf c out output capacitance outputs disabled; v o = 0v or 3.0v 9 9 pf i ccz total supply current outputs disabled 40 70 m a ordering information packages temperature range outside north america north america dwg number 48-pin plastic ssop type iii 40 c to +85 c 74alvt16373 dl av16373 dl sot370-1 48-pin plastic tssop type ii 40 c to +85 c 74alvt16373 dgg av16373 dgg sot362-1
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 3 logic symbol 3 2 1q0 1q1 1q2 6 5 1q3 47 46 44 43 1d0 1d1 1d2 1d3 48 1 9 8 1q4 1q5 1q6 12 11 1q7 41 40 38 37 1d4 1d5 1d6 1d7 1le 1oe 14 13 17 16 36 35 33 32 25 24 20 19 23 22 30 29 27 26 2q0 2q1 2q2 2q3 2d0 2d21 2d2 2d3 2q4 2q5 2q6 2q7 2d4 2d5 2d6 2d7 2le 2oe sa00044 pin description pin number symbol function 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 1d0 1d7 2d0 2d7 data inputs 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1q0 1q7 2q0 2q7 data outputs 1, 24 1oe , 2oe output enable inputs (active-low) 48, 25 1le, 2le enable inputs (active-high) 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage logic symbol (ieee/iec) 48 1en 1 ? 46 44 43 41 40 38 37 36 c3 2en c4 2 ? 1 24 25 47 35 33 32 30 29 27 26 3 2 5 6 8 9 11 12 13 14 16 17 19 20 22 23 sw00010 1oe 1le 2oe 2le 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d1 2d2 2d3 2d4 2d5 2d6 2d7 2d8 1q1 1q2 1q3 1q4 1q5 1q6 1q7 1q8 2q1 2q2 2q3 2q4 2q5 2q8 1d8 2q6 2q7 3d 4d pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1oe 1q0 1q1 gnd 1q2 1q3 1q4 1q5 gnd 1q6 1q7 2q0 2q1 gnd 2q3 v cc 2q4 v cc 2q2 2q5 gnd 2q7 2oe 2q6 1le 1d0 1d1 gnd 1d2 1d3 1d4 1d5 gnd 1d6 1d7 2d0 2d1 gnd 2d3 v cc 2d4 v cc 2d2 2d5 gnd 2d7 2le 2d6 sa00043
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 4 logic diagram e q d nd0 nq0 eq d nd1 eq d nd2 eq d nd3 eq d nd4 eq d nd5 eq d nd6 eq d nd7 nq1 nq2 nq3 nq4 nq5 nq6 nq7 nle noe sa00046 function table inputs internal outputs operating mode noe nle ndx register nq0 nq7 operating mode l l h h l h l h l h enable and read register l l l h l h l h latch and read register l l x nc nc hold h h l h x ndx nc ndx z z disable outputs h = high voltage level h = high voltage level one set-up time prior to the high-to-low e transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low e transition nc= no change x = don't care z = high impedance aoff o state = high-to-low e transition
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 5 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +4.6 v i ik dc input diode current v i < 0 50 ma v i dc input voltage 3 0.5 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +7.0 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions symbol parameter 2.5v range limits 3.3v range limits unit symbol parameter min max min max unit v cc dc supply voltage 2.3 2.7 3.0 3.6 v v i input voltage 0 5.5 0 5.5 v v ih high-level input voltage 1.7 2.0 v v il input voltage 0.7 0.8 v i oh high-level output current 8 32 ma i ol low-level output current 8 32 ma i ol low-level output current; current duty cycle 50%; f 1khz 24 64 ma d t/ d v input transition rise or fall rate; outputs enabled 10 10 ns/v t amb operating free-air temperature range 40 +85 40 +85 c
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 6 dc electrical characteristics (3.3v 0.3v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 3.0v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 3.0 to 3.6v; i oh = 100 m a v cc 0.2 v cc v v oh high - level out ut voltage v cc = 3.0v; i oh = 32ma 2.0 2.3 v v cc = 3.0v; i ol = 100 m a 0.07 0.2 v ol lowlevel out p ut voltage v cc = 3.0v; i ol = 16ma 0.25 0.4 v v ol low level out ut voltage v cc = 3.0v; i ol = 32ma 0.3 0.5 v v cc = 3.0v; i ol = 64ma 0.4 0.55 v rst power-up output low voltage 6 v cc = 3.6v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 3.6v; v i = v cc or gnd control pins 0.1 1 i i in p ut leakage current v cc = 0 or 3.6v; v i = 5.5v 0.1 10 m a i i in ut leakage current v cc = 3.6v; v i = v cc data p ins 4 0.5 1 m a v cc = 3.6v; v i = 0v data ins 4 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a bus hold current v cc = 3v; v i = 0.8v 75 130 i hold bus hold current data in p uts 7 v cc = 3v; v i = 2.0v 75 140 m a data inputs 7 v cc = 0v to 3.6v; v cc = 3.6v 500 i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 3.0v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc ; oe/oe = don't care 1 100 m a i ozh 3-state output high current v cc = 3.6v; v o = 3.0v; v i = v il or v ih 0.5 5 m a i ozl 3-state output low current v cc = 3.6v; v o = 0.5v; v i = v il or v ih 0.5 5 m a i cch v cc = 3.6v; outputs high, v i = gnd or v cc, i o = 0 0.04 0.1 i ccl quiescent supply current v cc = 3.6v; outputs low, v i = gnd or v cc, i o = 0 3.5 5 ma i ccz v cc = 3.6v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.05 0.1 d i cc additional supply current per input pin 2 v cc = 3v to 3.6v; one input at v cc 0.6v, other inputs at v cc or gnd 0.04 0.4 ma notes: 1. all typical values are at v cc = 3.3v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 3.3v 0.3v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. this is the bus hold overdrive current required to force the input to the opposite logic state. ac characteristics (3.3v 0.3v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3v 0.3v unit min typ 1 max t plh t phl propagation delay ndx to nqx 2 0.5 0.5 1.6 1.8 2.5 2.9 ns t plh t phl propagation delay nle to nqx 1 1.0 1.0 2.0 2.3 3.1 3.3 ns t pzh t pzl output enable time to high and low level 4 5 1.5 1.0 2.3 1.9 4.0 3.1 ns t phz t plz output disable time from high and low level 4 5 1.5 1.5 2.9 2.3 4.5 3.7 ns note: 1. all typical values are at v cc = 3.3v and t amb = 25 c.
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 7 dc electrical characteristics (2.5v 0.2v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 2.3v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 2.3 to 3.6v; i oh = 100 m a v cc 0.2 v v oh high - level out ut voltage v cc = 2.3v; i oh = 8ma 1.8 v v ol low-level out p ut voltage v cc = 2.3v; i ol = 100 m a 0.07 0.2 v ol low - level out ut voltage v cc = 2.3v; i ol = 24ma 0.3 0.5 v rst power-up output low voltage 7 v cc = 2.7v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 2.7v; v i = v cc or gnd control pins 0.1 1 i i in p ut leakage current v cc = 0 or 2.7v; v i = 5.5v 0.1 10 m a i i in ut leakage current v cc = 2.7v; v i = v cc data p ins 4 0.1 1 m a v cc = 2.7v; v i = 0 data ins 4 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a i h o ld bus hold current v cc = 2.3v; v i = 0.7v 90 m a hold data inputs 6 v cc = 2.3v; v i = 1.7v 10 m a i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 2.3v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc ; oe/oe = don't care 1 100 m a i ozh 3-state output high current v cc = 2.7v; v o = 2.3v; v i = v il or v ih 0.5 5 m a i ozl 3-state output low current v cc = 2.7v; v o = 0.5v; v i = v il or v ih 0.5 5 m a i cch v cc = 2.7v; outputs high, v i = gnd or v cc, i o = 0 0.04 0.1 i ccl quiescent supply current v cc = 2.7v; outputs low, v i = gnd or v cc, i o = 0 2.3 4.5 ma i ccz v cc = 2.7v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.04 0.1 d i cc additional supply current per input pin 2 v cc = 2.3v to 2.7v; one input at v cc 0.6v, other inputs at v cc or gnd 0.04 0.4 ma notes: 1. all typical values are at v cc = 2.5v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 2.5v 0.2v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. not guaranteed. 7. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. ac characteristics (2.5v 0.2v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v unit min typ 1 max t plh t phl propagation delay ndx to nqx 2 1.0 1.0 2.0 2.4 3.2 4.2 ns t plh t phl propagation delay nle to nqx 1 1.5 1.5 2.6 2.8 4.2 4.5 ns t pzh t pzl output enable time to high and low level 4 5 2.0 1.5 3.5 2.6 5.5 4.7 ns t phz t plz output disable time from high and low level 4 5 1.5 1.0 2.7 2.0 4.5 3.5 ns note: 1. all typical values are at v cc = 2.5v and t amb = 25 c.
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 8 ac setup requirements gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v v cc = 3.3v 0.3v unit min typ min typ t s (h) t s (l) setup time ndx to nle 3 0 1.5 0.7 0.2 0.5 0.8 0.2 0.2 ns t h (h) t h (l) hold time ndx to nle 3 0.5 1.5 0.2 0.7 0.8 1.0 0 0.2 ns t w (h) nle pulse width high 1 1.5 1.5 1.5 1.5 ns ac waveforms for all waveforms v m = 1.5v for v cc 3.0v; v m = v cc /2 for v cc 2.7v v m = 1.5v for v cc 3.0v; v m = v cc /2 for v cc 2.7v v x = v ol + 0.3v for v cc 3.0v; v x = v ol + 0.15v for v cc 2.7v v y = v oh 0.3v for v cc 3.0v; v y = v oh 0.15v for v cc 2.7v v m v m v m v m v m t w (h) t phl t plh nle nqx sw00163 3.0v or v cc whichever is less 0v v oh v ol waveform 1. propagation delay, enable to output, and enable pulse width ndx v m t plh t phl nqx v m v m v m sw00164 3.0v or v cc whichever is less 0v v oh v ol waveform 2. propagation delay for data to outputs note: the shaded areas indicate when the input is per- mitted to change for predictable output performance. v m ndx v m v m v m v m nle t s (h) t h (h) t s (l) t h (l) sw00165 v m 3.0v or v cc whichever is less 0v 0v 3.0v or v cc whichever is less waveform 3. data setup and hold times noe v m t pzh t phz nqx v m v m sw00166 0v v x v oh 3.0v or v cc whichever is less 0v waveform 4. 3-state output enable time to high level and output disable time from high level noe t pzl t plz 0v nqx v m v m v m sw00167 v ol v y 3.0v or v cc whichever is less 3.0v or v cc waveform 5. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 9 test circuit and waveforms pulse generator r t v in d.u.t. v out c l r l v cc r l open v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v or v cc / 2, whichever is less input pulse definition input pulse requirements family amplitude rep. rate t w t r t f 74alvt16 gnd 6v or v cc x 2 sw00162 test circuit for 3-state outputs switch position test switch t phz /t pzh gnd t plz /t pzl 6v or v cc x 2 t plh /t phl open definitions 3.0v or v cc whichever is less 10mhz 500ns 2.5ns 2.5ns r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators.
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 10 ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 11 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1mm sot362-1
philips semiconductors product specification 74alvt16373 2.5v/3.3v 16-bit transparent d-type latch (3-state) 1999 oct 18 12 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. print code date of release: 10-99 document order number: 9397-750-06516

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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